STM32WB30CEU5ATR

Ultra-low-power dual core Arm Cortex-M4 MCU 64 MHz, Cortex-M0+ 32 MHz with 512 Kbytes of Flash memory, Bluetooth LE 5.4, 802.15.4, Zigbee, Thread, Matter, AES-256

Parameters

Supply Voltage Min Volt	2.0
Supply Voltage Max Volt	3.6
Operating Temp Min Celsius	-10.0
Operating Temp Max Celsius	85.0
Operating Voltage Min Volt	2.0
Operating Voltage Max Volt	3.6
Core	Arm Cortex-M4
ECCN US	5A992.c
ECCN EU	NEC
Packing Type	Tape And Reel
RoHs compliant	Ecopack2
Grade	Industrial
Package Name	UFQFPN 48 7x7x0.55 mm

Description

The STM32WB50CG and STM32WB30CE multiprotocol wireless and ultra-low-power device embeds a powerful and ultra-low-power radio compliant with the Bluetooth® Low Energy SIG specification 5.4 or with IEEE 802.15.4-2011. It contains a dedicated Arm® Cortex®-M0+ for performing all the real-time low...
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The STM32WB50CG and STM32WB30CE multiprotocol wireless and ultra-low-power device embeds a powerful and ultra-low-power radio compliant with the Bluetooth^® Low Energy SIG specification 5.4 or with IEEE 802.15.4-2011. It contains a dedicated Arm^® Cortex^®-M0+ for performing all the real-time low layer operation.

The devices are designed to be extremely low-power and are based on the high-performance Arm^® Cortex^®-M4 32-bit RISC core operating at a frequency of up to 64 MHz. This core features a Floating point unit (FPU) single precision that supports all Arm^®single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) that enhances application security.

Enhanced inter-processor communication is provided by the IPCC with six bidirectional channels. The HSEM provides hardware semaphores used to share common resources between the two processors.

The devices embed high-speed memories (1 Mbyte of flash memory for STM32WB50xx, 512 Kbytes for STM32WB30xx, 128 Kbytes of SRAM for STM32WB50xx, 96 Kbytes for STM32WB30xx) and an extensive range of enhanced I/Os and peripherals.

Direct data transfer between memory and peripherals and from memory to memory is supported by seven DMA channels with a full flexible channel mapping by the DMAMUX peripheral.

The devices feature several mechanisms for embedded flash memory and SRAM: readout protection, write protection and proprietary code readout protection. Portions of the memory can be secured for Cortex^® -M0+ exclusive access.

The AES encryption engine, PKA, and RNG enable lower layer MAC and upper layer cryptography.

The devices offer a fast 16-bit ADC.

These devices embed a low-power RTC, one advanced 16-bit timer, one general-purpose32-bit timer, two general-purpose 16-bit timers, and two 16-bit low-power timers.

The STM32WB50CG and STM32WB30CE also feature standard and advanced communication interfaces, namely one USART (ISO 7816, IrDA, Modbus, and Smartcard mode), one I2C (SMBus/PMBus), one SPI up to 32 MHz.

The STM32WB50CG and STM32WB30CE operate in the -10 to +85 °C (+105 °C junction) temperature range from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving modes enables the design of low-power applications.

The devices include independent power supplies for analog input for ADC.

A V_BAT dedicated supply allows the device to back up the LSE 32.768 kHz oscillator, the RTC and the backup registers, thus enabling the STM32WB50CG and STM32WB30CE to supply these functions even if the main V_DD is not present through a CR2032-like battery, a Supercap or a small rechargeable battery.

The STM32WB50CG and STM32WB30CE are available in a 48-pin UFQFPN package.

Key features

Key features
Include ST state-of-the-art patented technology Radio 2.4 GHz RF transceiver supporting Bluetooth^® 5.4specification or IEEE 802.15.4-2011 PHY and MAC, supporting Thread 1.3 and Zigbee^® 3.0 RX sensitivity: -96 dBm (Bluetooth^® Low Energy at 1 Mbps), -100 dBm (802.15.4) Programmable output power up to +4 dBm with 1 dB steps Integrated balun to reduce BOM Support for 1 Mbps Support GATT caching Support EATT (enhanced ATT) Support advertising extension Dedicated Arm^® 32-bit Cortex^® M0+ CPU for real-time Radio layer Accurate RSSI to enable power control Suitable for systems requiring compliance with radio frequency regulations ETSI EN 300 328, EN 300 440, FCC CFR47 Part 15 and ARIB STD-T66 Support for external PA Available integrated passive device (IPD) companion chip for optimized matching solution (MLPF-WB-01E3) Ultra-low-power platform 2.0 to 3.6 V power supply – 10 °C to +85 °C temperature range 14 nA shutdown mode 700 nA Standby mode + RTC + 32 KB RAM 2.25 µA Stop mode + RTC + 128 KB RAM Radio: Rx 7.9 mA / Tx at 0 dBm 8.8 mA Core: Arm^® 32-bit Cortex^®-M4 CPU with FPU, adaptive real-time accelerator (ART™ Accelerator) allowing 0-wait-state execution from flash memory, frequency up to 64 MHz, MPU, 80 DMIPS and DSP instructions Performance benchmark 1.25 DMIPS/MHz (Drystone 2.1) 219.48 CoreMark^® (3.43 CoreMark/MHz at 64 MHz) Energy benckmark 303 ULPMark™ CP score Supply and reset management Ultra-safe, low-power BOR (brownout reset) with five selectable thresholds Ultra-low-power POR/PDR Programmable voltage detector (PVD) V_BAT mode with RTC and backup registers Clock sources 32 MHz crystal oscillator with integrated trimming capacitors (Radio and CPU clock) 32 kHz crystal oscillator for RTC (LSE) Internal low-power 32 kHz (±5%) RC (LSI1) Internal low-power 32 kHz (stability ±500 ppm) RC (LSI2) Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25% accuracy) High speed internal 16 MHz factory trimmed RC (±1%) 1x PLL for system clock, ADC Memories 1 MB flash memory with sector protection (PCROP) against R/W operations, enabling radio stack and application 128 KB SRAM, including 64 KB with hardware parity check 20x 32-bit backup register Boot loader supporting USART, SPI, I2C interfaces OTA (over the air) Bluetooth^® Low Energy and 802.15.4 update 1 Kbyte (128 double words) OTP Rich analog peripherals (down to 2.0 V) 12-bit ADC 2.13 Msps, up to 16-bit with hardware oversampling, 200 µA/Msps System peripherals Inter processor communication controller (IPCC) for communication with Bluetooth^® Low Energy and 802.15.4 HW semaphores for resources sharing between CPUs 1x DMA controller (7x channels) supporting ADC, SPI, I2C, USART, AES, timers 1x USART (ISO 7816, IrDA, SPI Master, Modbus and Smartcard mode) 1x SPI 32 Mbit/s 1x I2C (SMBus/PMBus^®) 1x 16-bit, four channels advanced timer 2x 16-bit, two channels timer 1x 32-bit, four channels timer 2x 16-bit ultra low power timer 1x independent Systick 1x independent watchdog 1x window watchdog Security and ID Secure firmware installation (SFI) for Bluetooth^® Low Energy and 802.15.4 SW stack 2x hardware encryption AES maximum 256-bit for the application, the Bluetooth^® Low Energy and IEEE802.15.4 HW public key authority (PKA) Cryptographic algorithms: RSA, Diffie-Helman, ECC over GF(p) True random number generator (RNG) Sector protection against R/W operation (PCROP) CRC calculation unit Die information: 96-bit unique ID IEEE 64-bit unique ID, possibility to derive 802.15.4 64-bit and Bluetooth^® Low Energy 48-bit EUI Up to 30 fast I/Os, 28 of them 5 V-tolerant Development support Serial wire debug (SWD), JTAG for the application processor Application cross trigger ECOPACK2 compliant package

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