Flat-rate $5.99 shipping worldwide throughout July - no code needed. Start your design today!Flat-rate $5.99 shipping worldwide throughout July - no code needed. Start your design today!Flat-rate $5.99 shipping worldwide throughout July - no code needed. Start your design today!Flat-rate $5.99 shipping worldwide throughout July - no code needed. Start your design today!
The STM32WL55/54xx long-range wireless and ultra-low-power devices embed a powerful and ultra-low-power LPWAN-compliant radio solution, enabling the following modulations: LoRa®, (G)FSK, (G)MSK, and BPSK.
The LoRa® modulation is available in STM32WLx5xx only.
These devices are designed to be extremely low-power and are based on the high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 48 MHz. This core implements a full set of DSP instructions. It is complemented by an Arm® Cortex®-M0+ microcontroller. Both cores implement an independent memory protection unit (MPU) that enhances the application security.
The devices embed high-speed memories (256-Kbyte Flash memory, 64-Kbyte SRAM), and an extensive range of enhanced I/Os and peripherals.
The devices also embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection and proprietary code readout protection.
In addition, the STM32WL55/54xx devices support the following secure services running on Arm® Cortex-M0+: unique boot entry capable, secure sub-GHz MAC layer, secure firmware update, secure firmware install and storage and management of secure keys.
These devices offer a 12-bit ADC, a 12-bit DAC low-power sample-and-hold, two ultra-low-power comparators associated with a high-accuracy reference voltage generator.
The devices embed a low-power RTC with a 32-bit sub-second wakeup counter, one 16-bit single-channel timer, two 16-bit four-channel timers (supporting motor control), one 32-bit four-channel timer and three 16-bit ultra-low-power timers.
These devices also embed two DMA controllers (7 channels each) allowing any transfer combination between memory (Flash memory, SRAM1 and SRAM2) and peripheral, using the DMAMUX1 for flexible DMA channel mapping.
The devices also feature the standard and advanced communication interfaces listed below: