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Mainstream Arm Cortex-M0 Access line MCU with 32 Kbytes of Flash memory, 48 MHz CPU, motor control
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2 kW two-channel interleaved PFC reference design based on the STNRGPF12 digital controller with dig
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High-Performance Arm Cortex-M7 MCU, 600MHz, 64KB Bootflash, 620KB SRAM, with DSP, cache, USB OTG FS,
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Rail-to-rail input/output 5V CMOS Op-Amp, micro-power (29uA), GBP=1.3MHz, small offset, single
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Ultra-low-power Arm Cortex-M0+ MCU with 192-Kbytes of Flash memory, 32 MHz CPU, AES
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Fully Integrated GPS/Galileo/Glonass/Beidou2/QZSS Receiver with embedded RF and in-package Flash
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Mainstream Arm Cortex-M0 Access line MCU with 32 Kbytes of Flash memory, 48 MHz CPU, motor control
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50 W wide-range high power factor flyback converter using the L6564